Semiconductor devices are always developing toward smaller feature sizes with higher densities of circuitry. When feature size is below 0.25 um, RC delay caused by the resistivity of metal traces and the parasitic capacitance of dielectric becomes the major key factor impacting the operation speed of semiconductor devices. Therefore, semiconductor industries have implemented copper traces in chips to replace the conventional Al/W or Al/Cu traces when feature sizes are below 0.13 um to increase the operation frequency of semiconductor devices so that copper processes have become the mainstream of multiple metal layers of high-end IC technology in the world. Since copper is an active metal, any copper ion from chips or substrates becomes the killing contaminant to the performance of Si materials and other dielectric materials. Once the semiconductor layers of Si chips are penetrated and contaminated by copper ions, the life cycles of minor carriers are shortened and the leakage current of devices increases. Furthermore, when copper ions penetrate into internal dielectric layer of IC chips, the breakdown electric fields are decreased with the increase of leakage current.
In the conventional chip packages, not only chips have copper circuitry but also substrates have many copper circuitry in different layers where normally a gold layer is disposed on the I/O pads of copper traces in substrates to prevent copper oxidation and to enhance electrical connections so that bonding wires can be used as electrical connection between chips and substrates. A barrier layer is formed between the gold layer and the copper circuitry to avoid inter-metallic diffusion between the gold layer and the copper layer. However, the barrier layer in substrate is only formed under I/O connecting pads and is very localized with a very thin thickness which can not effectively stop copper ions diffusing from the copper circuitry to the semiconductor layers of chips. Moreover, the copper ions of the chips also diffuse to the semiconductor layers leading to function failure of the chips, especially a lower chip disposed between an upper chip and the substrate which is more subject to function failure issues in the stacked package having chips using copper process.